1. Field of the Invention
The present invention relates to a signal extractor that extracts a determination signal for detecting an error in a bridge included in a complementary metal-oxide semiconductor (CMOS) large-scale integrated (LSI) circuit, for example, and an error detection apparatus and an error detection method that detect an error by using the determination signal.
2. Description of Related Art
Redundant errors such as bridge error due to high resistance short-circuit between source, drain or bulk in a CMOS LSI causes an increase in current consumption in the entire LSI, though it does not affect functional operation.
IDD Quiescent (IDDQ) test is a technique to detect such an error. Consumption current (power supply current) of each inverter in LSI is very low during stationary time when each CMOS inverter that forms the LSI does not perform switching. On the other hand, the power supply current level increases when an error such as a bridge error occurs in LSI. The IDDQ test makes use of this and measures a power supply current IDD, which is referred to herein also as the static current IDDQ, in the stationary time, thereby determining if an error exists or not.
Though consumption current of each CMOS inverter is low, the number of CMOS inverters in a chip is as many as several hundreds thousands to several millions in a large scale LSI, and consumption current that flows constantly is significantly high even in the stationary state. Further, with the miniaturization of a LSI manufacturing process, consumption current of each CMOS inverter is becoming higher and higher so that the entire consumption current reaches several tens mA order in some cases. Since the current that flows due to a bridge error is lower than original consumption current, it is unable to detect the bridge error completely merely in the stationary state. It is therefore necessary to supply a pattern that serves as a test signal to the LSI to activate a transistor and stop it at various points and measure a static current IDDQ at those times.
FIGS. 9A and 9B are block diagrams to describe abridge error. FIGS. 10A to 10C are block diagrams showing power supply current when a bridge error occurs and when it does not occurs. For example, in a CMOS inverter 201 composed of a P-channel transistor 202 and an N-channel transistor 203 that are connected between a power supply VDD and a ground GND, a bridge error 204 occurs between the power supply VDD and an output VOUT to keep connecting them as shown in FIG. 9A or it occurs between the ground GND and the output VOUT to keep connecting them as shown in FIG. 9B.
As described earlier, a power supply current IDD becomes high only in the switching operation and a static current IDDQ in the stationary state is very low when no bridge error occurs. When a bridge error occurs, on the other hand, the static current IDDQ is higher in a given stationary point compared with when no bridge error occurs.
For example, when the bridge error 204 occurs as shown in FIG. 9A, even if output VOUT of the CMOS inverter 201 is Low, which is, when input VIN is High and the P-channel MOSFET 202 is OFF and the N-channel MOSFET 203 is ON, leakage current flows into the output terminal from the power supply VDD through the bridge error 204. Thus, the power supply current IDDQ in standby state is substantially zero when no error exists as shown in FIG. 10B. When, on the other hand, the bridge error 204 exists, the power supply current IDDQ increases if the output VOUT of the CMOS inverter 201 is Low as shown in FIGS. 10A and 10C. If the output VOUT Of the CMOS inverter 201 is High, which is when the P-channel MOSFET 202 is ON and the N-channel MOSFET 203 is OFF, leakage current does not flow. Therefore, the static current IDDQ stays substantially zero even when the error exists.
Similarly, when the bridge error 205 occurs as shown in FIG. 9B, leakage current flows into the ground GND through the bridge error 205 if the output VOUT of the CMOS inverter 201 is High while leakage current does not flows if the output VOUT is Low. Therefore, the power supply current IDDQ increases in the standby state in this case as well. In this way, it is possible to detect a bridge error occurring in a circuit by fixing the output VOUT of the CMOS inverter 201 to High or Low and measuring a the static current IDDQ. Such a test method for detecting a bridge error in the CMOS inverter 201 is the IDDQ test.
On the other hand, an error detection apparatus for IC that is disclosed in Japanese Unexamined Patent Application Publication No. 2003-185698 uses a method for detecting an error by measuring power supply current during operation. By contrast with the static power supply current IDDQ, dynamic power supply current (consumption current) is referred to herein as operation current IDDT. This error detection apparatus detects an error by analyzing the frequency of a power supply current that flows through an integrated circuit under test when a test signal is applied thereto. The apparatus includes DC component removal means for removing DC components from a current observation signal of power supply current that flows through the integration current and extracting AC components only in order to keep low limiting resolution in spite of an increase in power supply current.
This error detection apparatus dynamically changes the circuit by switching test patterns in succession and acquires a change in operation current IDDT at this time by a sampling unit, thereby detecting if an error exists or not. This method measures the transition of the operation current IDDT with change in the circuit state. If a circuit is defective such as being inoperable, the operation current IDDT changes to a different state compared with nondefective. Then, spectrum analysis is performed using Fourier transform, thereby detecting the defective. By extracting AC component and removing AC component in the operation current IDDT at this time, it is possible to obtain higher resolution and thus improves the sensitivity of eror detection.
The present invention, however, has recognized that the IDDQ test or the technique disclosed in Japanese Unexamined Patent Application Publication No. 2003-185698 described above have the following problems. First, the IDDQ test is incapable of accurate measurement since the current that is assumed to flow in error mode is too low with respect to the operation current. The operation current can be several tens mA order in some devices since each leakage current increases to as high as several tens to hundreds nA with miniaturization of the LSI manufacturing process. On the contrary, the current that flows through a bridge error can be as low as several hundreds μA or below.
Generally, the current measuring accuracy of a tester is within about 0.2% from a measurement range. Thus, though 100 mA range, for example, is needed to measure operation current of several tens mA order, the accuracy of this range is 100 mA*0.2%=200 μA. Therefore, if the current flowing to a bridge error is 100 μA, it is unable to detect the presence of the bridge error accurately with this accuracy.
On the other hand, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2003-185698 continuously switches test patterns to switch between ON and OFF constantly without fixing the state of the transistor to ON or OFF state. It converts a change in current into a spectrum power by using Fourier transform to see if there is a difference from nondefective, thereby determining whether it is defective or not. Thus, this technique observe the power supply current (IDDT) that flows when applying a test signal to an integrated circuit and analyzes it in frequency domain so as to detect abnormal power supply current due to an error in a short time. It is thus difficult to detect a bridge error that occurs in any transistor in an integrated circuit under test.
Thus, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2003-185698 performs function testing to find a defect that one transistor of a CMOS inverter does not turns ON or OFF and so on, for example, by measuring dynamic operation current. It therefore switches test patterns constantly to change the state of a circuit dynamically, so that the CMOS inverter 201 always switches between High and Low. Therefore, leakage current (abnormal current) due to a bridge error flows and stops during measuring power supply current. Since the abnormal current due to a bridge error is very low current that is detectable when the CMOS inverter 201 becomes a fixed (static) state of High or Low, it is difficult to detect the abnormal current due to a bridge error with such a measuring technique that switches the CMOS inverter 201 between High and Low.
Recent LSI is required to reduce leakage current due to a bridge error as low as possible in order to further lower the power consumption particularly when it is used for a portable information equipment or the like. It is desirable to detect such a bridge error also for the purposes of improvement in product quality, elimination of life-time defect, increase in reliability, reduction in total test costs and so on.